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| C8051F221 25 MIPS, 8 kB Flash, 8-Bit ADC, 32-Pin Mixed-Signal MCU Analog Peripherals 8-Bit ADC High-Speed 8051 C Core - - 1/2 LSB INL; no missing codes Programmable throughput up to 100 ksps 32 external inputs (each port I/O can be configured as an ADC input onthe-fly) Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator VREF from external pin or VDD Programmable hysteresis Configurable to generate interrupts or reset Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler; up to 21 interrupt sources 256 bytes data RAM 8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are reserved) 22 port I/O; all are 5 V tolerant Hardware SPITM and UART serial ports available concurrently 3 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Internal programmable oscillator: 2-16 MHz External oscillator: Crystal, RC, C, or Clock Can switch between clock sources on-the-fly 32-pin LQFP (standard lead and lead-free packages) Lead-free package: C8051F221-GQ Standard package: C8051F221 Memory Two comparators Digital Peripherals VDD Monitor and Brown-out Detector On-Chip JTAG Debug On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets Fully compliant with IEEE 1149.1 specification Typical operating current: 9 mA at 25 MHz Typical stop mode current: <0.1 uA Clock Sources Package Ordering Part Numbers Supply Voltage: 2.7 to 3.6 V Temperature Range: -40 to +85 C VDD GND Analog/Digital Power Port 0 Latch UART Timer 0 Timer 1 Timer 2 P 0 M U X P 0 D r v P0.0/TX P0.1/RX P0.2//INT0 P0.3//INT1 P0.4/T0 P0.5/T1 P0.6/T2 P0.7/T2EX TCK TMS TDI TDO RST JTAG Logic Debug HW Reset 8 0 5 1 C o r e 8 kB FLASH 256 byte RAM Port 1 Latch CP0 CP0+ CP0 P 1 M U X P 1 D r v CP0CP1+ CP1 CP1 P1.0/CP0+ P1.1/CP0P1.2/CP0 P1.3/CP1+ P1.4/CP1P1.5/CP1 P1.6/SYSCLK P1.7 VDD Monitor External Oscillator Circuit Internal Oscillator CP1SYSCLK WDT Port 2 Latch SPI XTAL1 XTAL2 SFR Bus P 2 M U X P 2 D r v P 3 System Clock P2.0/NSS P2.1/MISO P2.2/MOSI P2.3/SCK P2.4 P2.5 Port 3 Latch D r v 8-bit 100 ksps ADC VDD PGA A M U X AIN0-AIN31 VREF General Purpose Copyright (c) 2005 by Silicon Laboratories 5.5.2005 C8051F221 25 MIPS, 8 kB Flash, 8-Bit ADC, 32-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = -40 to +85 C, VDD = 2.7 V unless otherwise specified unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Digital Supply Voltage Digital Supply Current Clock = 25 MHz with CPU active Clock = 1 MHz Clock = 32 kHz Digital Supply Current Oscillator not running (shutdown) Digital Supply RAM Data Retention Voltage CPU & DIGITAL I/O PORTS Clock Frequency Range Port Output High Voltage IOH = -3 mA, Port I/O push-pull Port Output Low Voltage IOL = 8.5 mA Input High Voltage Input Low Voltage SPI Bus Clock Frequency fCLK=MCU Clock; SPI in Master Mode A/D CONVERTER Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal to Noise Ratio Throughput Rate Input Voltage Range COMPARATORS Response Time | CP+ - CP- | = 100 mV Input Voltage Range Input Bias Current Input Offset Voltage MIN 2.7 9 0.4 18 7 1.5 DC VDD - 0.7 0.8 x VDD 0.2 x VDD fCLK/2 8 1/2 1/2 49 0 4 -0.25 -5 -10 0.001 VDD + 0.25 +5 +10 100 VREF 25 0.6 TYP MAX 3.6 UNITS V mA mA A A V MHz V V V V MHz bits LSB LSB dB ksps V s V nA mV Package Information D D1 A MIN NOM MAX (mm) (mm) (mm) 1.60 0.15 C8051F226DK Development Kit A1 0.05 E1 E A2 1.35 1.40 1.45 b 0.30 0.37 0.45 9.00 7.00 0.80 9.00 7.00 - 32 D D1 1 PIN 1 IDENTIFIER A2 e A b A1 e E E1 General Purpose Copyright (c) 2005 by Silicon Laboratories 5.5.2005 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders |
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